Silicon IPs

We offer proven, integration-ready IP designs for ASIC and FPGA projects, delivering reliable performance at competitive costs. We also develop custom IP solutions tailored to each client’s specific requirements.

Close-up of an orange circuit board with an IC chip

AES Encoder/Decoder

Implements reference design specified in NIST FIPS 197
Supports 5 different block cipher modes
Supports 128, 192 and 256-bit key widths
128-bit data input
Encrypt and Decrypt both supported and can be done in parallel

JPEG Encoder

Input matrix supported stream format YCbCr 4:4:4
8 bits input and output bitstream
Fixed quantization table and compression level
Single-stage header module
Scan encoder performs Discrete cosine transform, Quantization, Run-length encoding

JPEG encoder icon

SHA2

Reference design from FIPS 180-4 Secure Hash Standard
Supported block sizes 512- and 1024-bit (SHA2-256 and SHA2-512 respectively)
Message digest sizes supported are 256- and 512-bit

BCH Encoder/Decoder

BCH encoder use linear-feedback shift register (LFSR) computation
BCH decoder with reduced logic
Block size from 8- to 256-bit
Encode and Decode both supported

JPEG Decoder

8 bits input and output bitstream
Output data format is YCbCr 4:4:4
Decoder performs Run-length decoding, Dequantization, Inverse Discrete cosine transform

JPEG decoder icon

SHA3

Reference design from FIPS 202 Permutation-based Hash and Extendable-output Functions
Support input block is flexible and up to 1600-bit
Message digest size supported is 256-bit